ARYABHAT- Analog Reconfigurable Technology and Bias-scalable Hardware for AI Tasks

Chetan Singh Thakur

PI: Prof Chetan Singh Thakur, IISc Bengaluru

Team Members: Pratik Kumar, Ankita Nandi, Muthiah S, Prof. Shantanu Chakrabartty, Prof. Chetan Singh Thakur

The project ARYABHAT presents a new approach, utilizing analog computing for designing resilient and scalable machine learning systems for AI at the edge. ARYABHAT is India’s first analog AI accelerator chipset, which addresses the challenges associated with conventional analog designs in creating large-scale analog accelerated chipset. The project starts by first proposing a robust mathematical framework and its design methodologies to create modular, programmable, and scalable analog processing elements for machine-learning circuits and systems. Subsequently, the framework was extended to develop an end-to-end Analog AI Compute Ecosystem.

ARYABHAT, taped out on the TSMC 180nm technology node, is a bias scalable analog accelerator meaning it can perform at high performance (strong inversion regime) as well as the low power (subthreshold) modes. At the core of this computational architecture are the eight reconfigurable tiles, each housing a matrix of 13 × 12 processing elements that support near memory compute. A custom analog interconnect fabric which enables programmability of the processing elements, allowing the chip to be reconfigured to varying circuit configurations. The broader application of this work enables the design of analog systems for machine learning, which are invariant to transistor operating regimes, modular just like digital designs, robust to non-idealities of devices, and simultaneously process technology scalable.

This project is motivated by the concept of utilizing analog technology to overcome challenges faced by current machine learning and neural network hardware. The efforts focused on unlocking new possibilities for high-performance machine learning systems, pushing the boundaries of what is currently achievable.

Keywords:
Analog AI accelerator, Bias/process scalable analog circuits, Reconfigurable analog Processor, Analog computing

Reference:

Pratik Kumar, Ankita Nandi, Shantanu Chakrabartty, and Chetan Singh Thakur, “Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Jan. 2023. DOI: 10.1109/JETCAS.2023.3234570.
Pratik Kumar, Ankita Nandi, Shantanu Chakrabartty, and Chetan Singh Thakur, “Process, Bias, and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 70, no. 1, pp. 128–141, Nov. 2022. DOI: 10.1109/TCSI.2022.3216287.
Pratik Kumar, Ankita Nandi, Ayan Saha, Kurupati Sai Pruthvi Teja, Ratul Das, Shantanu Chakrabartty, and Chetan Singh Thakur, “ARYABHAT: A Digital-Like Field Programmable Analog Computing Array for Edge,” IEEE Transactions on Circuits and Systems I (TCAS-I), accepted Jan. 2024. DOI: 10.1109/TCSI.2024.3349776.
Ankita Nandi, K. Gandhi, M. P. Singh, S. Chakrabartty, and C. S. Thakur, “KALAM: ToolKit for Automating High-Level Synthesis of Analog Computing Systems,” Proceedings of the IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 2025.

Patent:

“A Reconfigurable and Scalable Multi-Core Analog Computing Chip”, Indian Provisional Patent Application No. 202141054561, filed on 25th November 2021.

Group Website:

Neuronics Lab – IISc DESE