RAMAN: An AI Co-Processor for Edge Computing

Chetan Singh Thakur

PI: Prof Chetan Singh Thakur, IISc Bengaluru

Key Team Members: Dr. Adithya Krishna, Dr. Mahesh Mehendale, Prof. Chetan Singh Thakur

Researchers at the Department of Electronic Systems Engineering, IISc, led by Chetan Singh Thakur, have developed an AI co-processor called RAMAN, or Re-configurable And sparse tinyML Accelerator for infereNce. RAMAN is an indigenous low-power AI co-processor designed for edge computing applications. The researchers chose to name it RAMAN as a tribute to the Nobel laureate CV Raman, the first Indian Director of IISc.

RAMAN can be configured to run ML models for various applications such as object recognition, speech identification, brain-computer interfaces, and so on. It can easily be adapted to run diverse ML models for low-power inference applications. The RAMAN accelerator is designed to leverage data and weight sparsity to deploy deep neural networks at the edge, ensuring low power consumption, minimal storage requirements, and reduced processing latency. Conducting machine learning inference directly on edge devices offers numerous advantages, including decreased latency, heightened data privacy and security, and optimised bandwidth utilisation.

RAMAN incorporates a novel dataflow to reduce memory access. It supports variable precision quantization of both weights and activations. RAMAN performs memory optimisation, such as peak activation memory reduction, by leveraging cache to reduce memory size.

RAMAN, therefore, serves as a versatile AI co-processor tailored for edge applications, capable of integration within larger Systems-on-Chips akin to ARM IPs. The team has demonstrated RAMAN’s various applications in vision, BCI, and acoustics.

Demonstrating various applications of RAMAN

REFERENCES:

A. Krishna, S. R. Nudurupati, D. G. Chandana, P. Dwivedi, A. van Schaik, M. Mehendale, and C. S. Thakur, “RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge,” IEEE Internet of Things Journal, 2024.
A. Krishna, V. Ramanathan, S. S. Yadav, S. Shah, A. van Schaik, M. Mehendale, and C. S. Thakur, “A Sparsity-driven tinyML Accelerator for Decoding Hand Kinematics in Brain-Computer Interfaces,” IEEE Biomedical Circuits and Systems Conference (BioCAS), 2023.
A. Krishna, H. Shankaranarayanan, H. P. O. Hitesh, C. Anand, A. van Schaik, M. Mehendale, and C. S. Thakur, “LIVE DEMO: TinyML Acoustic Classification using RAMAN Accelerator and Neuromorphic Cochlea,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2023.
A. Krishna, S. Debnath, A. van Schaik, M. Mehendale, and C. S. Thakur, “Neural Signal Compression using RAMAN tinyML Accelerator for BCI Applications,” arXiv preprint arXiv:2504.06996, 2025.
A. Krishna et al., “TinyML Acoustic Classification using RAMAN Accelerator and Neuromorphic Cochlea,” 2023 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PRIMEAsia), Hyderabad, India, 2023.

Demo Links:

RAMAN Accelerator Overview

Neuronics Lab – RAMAN Accelerator

YouTube Demo – TinyML Acoustic Classification

Watch on YouTube

YouTube Demo – Neural Signal Compression for BCI Applications

Watch on YouTube